The manufacture of integrated circuits includes the packaging of the semiconductor chip. FIGS. 1, 2 and 3 illustrate a conventional method for making a semiconductor package. Referring to FIG. 1, a lead frame is provided. The lead frame 1 includes at least one drain pin 11, at least one source pin 13 and at least one gate pin 14. The drain pin 11, source pin 13 and gate pin are connected to a frame (not shown) by corresponding extensions 12. The source pin 13 and the gate pin 14 face a side of the drain pin 11, and a space exists between the source pin 13 and the side of the drain pin 11 and between the gate pin 14 and the side of the drain pin 11.
Referring now to FIG. 2, at least one chip 2 is provided. The chip 2 has an upper surface 21 and a lower surface (not shown). The upper surface 21 has a source conductive region 22 and a gate conductive region 23. The lower surface has a drain conductive region (not shown). The chip 2 is disposed so that the drain conductive region is electrically connected to the drain pin 11.
Referring now to FIG. 3, a wiring process is performed. A first wire 31 is used to connect the source pin 13 of the lead frame 1 and the source conductive region 22 of the chip 2, and a second wire 32 is used to connect the gate pin 14 of the lead frame 1 and the gate conductive region 23 of the chip 2. The method may then continue with a molding process and a cutting process to further form the semiconductor package.
The conventional method for making the semiconductor package has the following disadvantages. The first wire 31 and the second wire 32 are gold wires, so the material cost is high. Moreover, during the wire bonding process, a wiring machine is used to form the first wire 31 and the second wire 32 one by one, which is time consuming. Further, a certain space must be reserved between the first wire 31 and the second wire 32 for the movement of a wiring head of the wiring machine, so that the space between the first wire 31 and the second wire 32 cannot be effectively narrowed. If the size of the chip 2 is reduced to a certain degree, the conventional method is not applicable.
Therefore, there is a continuing need to provide an improved semiconductor package and a method for making the same, to solve the above problems.